A display device which is used in a computer, a point of sale (POS) terminal or like equipment includes a refresh memory to store data to be displayed. The data to be displayed is written into the refresh memory by an external central processing unit (CPU) and the data thus written into the refresh memory is read out by a display controller (DC) which is provided within the display device to be displayed on a cathode ray tube (CRT) or a liquid crystal display (LCD).
In a conventional cathode ray tube (CRT) display device, it is generally known that it is necessary to repeatedly refresh the screen on the CRT, normally on the order of 50-60 times per second, in order to maintain a continuously displayed state and in the manner wherein a controller sequentially reads out all addresses in a refresh memory. In addition, it is also necessary to access the refresh memory from the central processing unit (CPU) for any modification of the screen-displayed content and for other purposes. It is in a normal operation that the display controller (DC) always accesses the refresh memory to read out the display data therefrom. In addition, it is also necessary to access the refresh memory from the external CPU in order to change the contents to be displayed (modifications) or in order to read out the display data to the outside world. Under the above mentioned circumstances, simultaneous access to the refresh memory from the CPU and the display controller (DC) sometimes causes a problem wherein the screen has a flash or a flicker and the contents to be displayed cannot be changed. However, competitive accessing the refresh memory from or by the central processing unit (CPU) and the display controller (DC) causes the flash or flicker to be generated or present on a portion of the screen.
In order to avoid competitive accessing as mentioned above, conventionally there have been proposed an asynchronous access method and a synchronous access method. Since the present invention concerns and deals with the synchronous access method, a description of the asynchronous access method is not included herein. In the synchronous access method, the time required to display one character (one character clock period) is one half the normal time. In this regard, one half of the time the CPU is allowed to access the refresh memory and the other half of the time the display controller (DC) is allowed to access the refresh memory in an alternating arrangement as assigned to the CPU and the display controller.
In order to avoid this flashing or flickering on the screen, a system clock has been developed in a manner so as to access the memory from the central processing unit during the time when the system clock is at a low level, and to access the memory from the display controller during the time when the system clock is at a high level. In the alternating arrangement of the CPU and the display controller (DC), it is seen that no competitive accessing occurs.
A synchronous access method as mentioned above is described in detail in the bulletin of Japanese Patent Application No. 109217/82 as a prior art document. In the above mentioned synchronous access method, the one character clock period is halved to access the refresh memory. In other words, the refresh memory is accessed in one half of the time required to display one character. Accordingly, in order to avoid such associated problems, it is necessary that high speed elements which are operable in one half of the time and which are required for the operation of conventional elements should be used for the refresh memory and for any peripheral circuits thereof.
Recently, it is known that a one-chip (packaged IC) CPU, a one-chip display controller (DC), and a one-chip memory, which devices or elements operate at a relatively high speed, have been marketed and are available at relatively low costs. Accordingly, the use of the high speed, single chip elements which came into question in the conventional synchronous access method causes no serious problem.
However, a character display system of the sychronous access method in which the above mentioned one-chip central processing unit (CPU) and the one-chip display controller (DC) are employed can be associated with or be subject to a problem in the operation of the system.
The character display system of the above mentioned type which is subject to such problem will now be described. The one-chip CPU prepares its own system clock therewithin and the one-chip display controller also prepares its own memory clock therewithin. In the CPU, the memory clock is similar to the system clock in the manner that it is a clock for controlling the timing of accessing the refresh memory, so that such clock is hereinafter referred to as the system clock. The CPU and the display controller (DC) are so constructed as to access the refresh memory, respectively, when each of their own system clocks is high. Accordingly, the operation is initialized so that the system clocks are 180.degree. out of phase with each other in order to avoid simultaneous accessing of the refresh memory by the CPU and the display controller. However, the clocks are prepared or initialized independently of each other by their respective counters within the CPU and the display controller, so that one of the system clocks sometimes may be inverted by reason of the influence of electrostatic discharge noise and the like. It is now assumed that noise occurs at a certain point and only the system clock of the display controller is inverted. The system clock is again inverted at the next rising edge of the basic clock, so that the CPU clock becomes in phase with the display controller clock. As a result, the access timings of the CPU and the display controller (DC) entirely coincide with each other. The coincidence of both system clocks causes such a problem that neither the CPU nor the display controller can access the refresh memory. In a conventional display, once such coincidence as mentioned above occurs, the display is temporarily reset to re-initialize both clocks. However, the resetting of the display during the time that data is being written from the CPU causes error in writing. As a result, such a problem requires that an operator check and correct the contents to be displayed after resetting the display.
In this connection, it is to be noted that the above mentioned Japanese Patent Application No. 109217/82 does not touch on a situation wherein both system clocks coincide with each other. In addition, as far as the inventors of the present invention have knowledge, no conventional technique and/or prior art which intend to solve the above mentioned problem have been found.
In the prior art and as another proposed solution to these draw-backs, there has been proposed a technique described in Japanese Laid-Open Patent Specification No. 66,989/83 wherein reference clocks in the central processing unit and the cathode ray tube controller are synchronized in alternating manner. This alternating manner is arranged so as to permit the memory access from the CPU only during the time when the reference clock of the CRT controller is at a low level, and to permit the memory access from the CRT controller only during the time when the reference clock of the controller is at a high level, thereby avoiding the competitive accessing from or by the CPU and the CRT controller. However, in this arrangement, the reference clock in the CRT controller is also divided into halves so as to assign individual halved periods as access time of the CPU and the CRT controller, respectively. As to refresh memory access and the associated peripheral circuit elements, it was necessary to use high speed elements capable of operating at least in a period which is one-half the conventional period, in an overall arrangement similar to that described above. Further, the reference clocks of the CPU and the CRT controller have been controlled so as to operate in synchronized manner in order to avoid such competitive accessing with the result that the structure of the control unit and the peripheral units was complicated or complex in nature.
Further documentation in the field of video display systems includes U.S. Pat. No. 4,237,543, issued to Y. Nishio et al. on Dec. 2, 1980, which discloses a microprocessor controlled display system having a data control unit including a microprocessor and an associated memory, a refresh memory unit connected to the data control unit through an address bus and a data bus, and a video control unit for accessing display data stored in the refresh memory unit by a timing control unit to produce a video signal. The refresh memory unit comprises memories sectioned by byte, an I/O controller which receives a read/write control signal to indicate whether the access by the data control unit is read access or write access, and an access memory specifying signal to indicate one or two byte memory access to produce an I/O control signal, and a memory controller responsive to the I/O signal to control data access to the memories.
U.S. Pat. No. 4,379,293, issued to C. Boisvert et al. on Apr. 5, 1983, discloses a CRT controller connected to a processor and having a refresh address generator to refresh display on the CRT, an update address generator to update information in refresh memory, and a control circuit for connecting the update address generator and the refresh address generator to refresh the memory so that only one of the generators has control of the refresh memory at a time.
U.S. Pat. No. 4,388,621, issued to S. Komatsu on Jun. 14, 1983, discloses a drive circuit for a character and graphic display device wherein a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator is extended and a time period during which the RAM is connected to a CPU is shortened without changing the period. This clock signal is used to acutate a switching circuit for the RAM.
U.S. Pat. No. 4,468,662, issued to K. Tanaka on Aug. 28, 1984, discloses a display apparatus having a picture memory with characters to be displayed on a CRT display monitor, a CPU of a controller for the picture memory, and a CRT controller for generating timing signals.
U.S. Pat. No. 4,482,979, issued to G. A. May on Nov. 13, 1984, discloses a video computing system with automatically refreshed memory connected to a CRT. A CRT controller is connected to the memory and a CPU operates on an alternating, two phase fetch and execute cycle.
U.S. Pat. No. 4,485,378, issued to K. Matsui et al. on Nov. 27, 1984, discloses display control apparatus wherein a refresh memory is used such that the respective areas thereof storing portions of the character are addressed in synchronism with the period of a character clock.
U.S. Pat. No. 4,511,965, issued to B. Rajaram on Apr. 16, 1985, discloses a video random access memory (RAM) accessing system for resolving the contention between the CPU and the CRT controller in accessing the memory. The CPU-CRT controller accessing sequence is modified to provide a CPU access period between successive CRT controller access periods.
And, U.S. Pat. No. 4,581,611, issued to C. C. Yang et al. on Apr. 8, 1986, discloses a character display system including a CRT of long persistence time along with a control unit, a CPU and a CRT controller. A video inhibit signal is generated for a predetermined period of time by the control unit to avoid flicker or flashing on the screen of the CRT during refreshing.